1. Field of the Invention
The present invention relates to an electrically reprogrammable non-volatile semiconductor memory device or electrically erasable programmable read-only memory (EEPROM), and particularly relates to the non-volatile semiconductor memory device which includes therein a charge-pump circuit for generating a high voltage necessary for a write/erase operation of the memory device and can be operated by a single power source.
2. Description of the Related Art
As an example of an EEPROM which is capable of performing write/erase using a single power source, for instance, Vcc=5 V, there is known a NAND type EEPROM. The NAND type EEPROM has a plurality of memory cells which commonly share a source and drain neighboring to each other and are arrayed in series so as to form a unit thereof and connected to a bit line through a selection transistor provided between the bit line and the NAND unit. In general, the memory cell has a FETMOS (Field Effect Transistor Metal-Oxide-Semiconductor) structure. The memory cell is, for example, an n channel type and the memory cell array is integrated in a p type well formed on an n type substrate or a p type substrate.
In the EEPROM such as a NAND type EEPROM, a voltage higher than a power supply voltage is usually applied at the time of write/erase operation so that a charge level of a charge storage layer is controlled by a tunnel current or a hot electron injection so as to store data.
For example, a write/erase of data for the above-mentioned NAND type EEPROM is operated as follows. Data writing is performed in the order from the memory cell farthest from the bit line. A high voltage Vpp of, for instance, approximately 20V is applied to a control gate of a selected memory cell, an intermediate potential VppM of, for instance, approximately 10V is applied to a gate of the selection transistor and the control gate of a memory cell located further in the bit line side, and a 0V or the intermediate potential is applied to the bit line in accordance with the data to be stored. When the 0V is applied to the bit line, the potential is transferred to a drain of the selected memory cell, so that an electron injection or tunnel phenomenon occurs from the drain into a floating gate. Thereby, a threshold of the selected memory cell is shifted to a positive direction. Such state is denoted as "1", for instance. When the intermediate potential is applied to the bit line, there will not be caused the electron injection or the tunnel phenomenon. Therefore, the threshold of the selected memory cell is not shifted and remains negative. This state is denoted as "0". Data erasing is carried out simultaneously against entire memory cells in the NAND cell. In other words, all of control gates and selection gates are set to 0V and the bit line as well as the source line are set to a floating state, and a high voltage of, for instance, 20V is applied to the p type well on the p type substrate. Consequently, electrons of the floating gate in every memory cell are discharged into the p type well or the p type substrate. Accordingly, the threshold of every memory cell is shifted to a negative direction.
As described above, even in an EEPROM operated by a single power source, it is generally necessary to generate a voltage, such as Vpp, higher than the power supply voltage. Therefore, the high voltage is conventionally generated using a charge-pump circuit. However, a current supply capacity of the charge-pump circuit generally declines as the power supply voltage decreases. The charge-pump circuit is usually driven by a ring oscillator. An oscillating frequency of the ring oscillator also declines as the power supply voltage decreases. As a result, referring to FIG. 1, in the charge-pump circuit which is designed to operate by a minimum power supply voltage, the charge-pump circuit has a current supply capacity which is well beyond the necessary capacity in case of a maximum power supply voltage value.
Thus, there has been a problem where a power supply has been unnecessarily wasted due to fluctuation of current supply capacity of the charge-pump circuit caused by the fluctuation of the power supply voltage at the time of write/erase.